The invention relates to a method of forming a gate line of a semiconductor device and, more particularly, to a method of forming a gate line of a semiconductor device, wherein when an etch process for forming a gate line is performed, a loading effect is improved, thereby enhancing the operating speed of a semiconductor device.
A semiconductor device is divided into a cell array area and a peripheral (“peri”) area outside the cell array area. In the case of a NAND flash memory device, a plurality of string structures is repeatedly arranged in the cell array area. Each of the string structures includes a source select transistor, a drain select transistor, and a plurality of memory cells connected in series between the source select transistor and the drain select transistor and configured to store data. Memory cells included in the cell array area and transistors constituting a circuit for driving the select transistors are formed in the peri area.
The memory cells, the select transistors, and the transistors of the peri area are supplied gate signals via gate lines. More specifically, the gate lines include a word line for supplying a gate signal to the memory cell, a select line for supplying a gate signal to the select transistor, and a gate line for supplying a gate signal to the transistor of the peri area. In general, the gate lines in the cell array area are denser than the gate lines in the peri area.
The gate lines are formed by etching a conductive layer for the gate lines, the conductive layer being formed over a semiconductor substrate, using a hard mask pattern as an etch barrier. With ongoing increases in the degree of integration of semiconductor devices, in order to improve the operating speed of a semiconductor device, such as the program speed and the reading speed, by lowering the resistance (Rs) of a gate line, there has been active development of a scheme in which material with low resistivity is stacked over a polysilicon layer as a conductive layer for the gate line. As part of such development, research has been conducted on a scheme for replacing tungsten silicide (WSix), which formerly was deposited on the polysilicon layer as the conductive layer for the gate lines, as tungsten (W), cobalt silicide (CoSix) or nickel silicide (NiSix) with low resistivity. However, tungsten, cobalt silicide, and nickel silicide have low stability as compared with tungsten silicide and require further development, since they have not been verified regarding deposition or etch methods.
Accordingly, there has been continuing development on methods of lowering the resistance of the conductive layer for the gate line using tungsten silicide having secured stability. As a result, a method of increasing the thickness of the tungsten silicide layer has been developed. However, the tungsten silicide layer is problematic in that a loading effect, which is generated according to a density difference of gate lines upon etching since the etch selectivity between the tungsten silicide layer and underlying polysilicon is low, becomes severe.
The tungsten silicide layer is also problematic in that the loading effect becomes worse when layer thickness increases. Consequently, when a thick tungsten silicide layer is used, the loading effect becomes severe, which consequently is likely to result in damage to underlying layers.
More specifically, hard mask patterns used to pattern gate lines are formed more densely in the cell array area than in the peri area. If the tungsten silicide layer is etched using the hard mask patterns as an etch barrier, the tungsten silicide layer of the peri area is etched anterior to the tungsten silicide layer of the cell array area and separated on a per-gate-line basis, so an underlying layer is exposed. The layer exposed in the peri area may be damaged during an etch process for separating the tungsten silicide layer of the cell array area on a per-gate-line basis. Consequently, after the tungsten silicide layer is etched, the underlying layers (for example, the polysilicon layer) remain thinner in the peri area than in the cell array area due to the damage of the layer exposed in the peri area.
Accordingly, even while an etch process for separating a layer under the tungsten silicide layer on a per-gate-line basis is performed, the tungsten silicide layer of the peri area is first etched and therefore a layer (a dielectric layer) under the tungsten silicide layer can be exposed and damaged. Furthermore, even an active area provided in the semiconductor substrate of the peri area may be damaged. Damage to the active area causes low reliability of a semiconductor device. Accordingly, there is a need for a scheme, which can increase the thickness of the tungsten silicide layer by improving the loading effect.